MUSTANG: state assignment of finite state machines targeting multilevel logic implementations

In this paper, we address the problem of the state assignment for synchronous finite state machines (FSM), targeted towards multilevel combinational logic and feedback register implementations. Optimal state assignment aims at a minimum area implementation. All previous work in automatic FSM state assignment has been directed at programmable logic array (PLA) i.e., two-level logic implementations. In practice, most large FSM's are not synthesized as a single PLA for speed and area reasons-multilevel logic implementations are generally used for smaller delay and area. In this paper, we present state assignment algorithms that heuristically maximize the number of common cubes in the encoded network so as to minimize the number of literals in the resulting combinational logic network after multilevel logic optimization. We present results over a wide range of benchmarks which prove the efficacy of our techniques. Literal counts averaging 20-40 percent less than other state assignment programs have been obtained.